Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
inst2|irq_mapper |
6 |
28 |
2 |
28 |
32 |
28 |
28 |
28 |
0 |
0 |
0 |
0 |
0 |
inst2|width_adapter_003|uncompressor |
37 |
4 |
0 |
4 |
28 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
inst2|width_adapter_003 |
90 |
3 |
0 |
3 |
112 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst2|width_adapter_002 |
117 |
3 |
0 |
3 |
85 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst2|width_adapter_001|uncompressor |
37 |
4 |
0 |
4 |
28 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
inst2|width_adapter_001 |
99 |
3 |
0 |
3 |
112 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst2|width_adapter |
117 |
3 |
0 |
3 |
94 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst2|rsp_xbar_mux_001|arb|adder |
48 |
24 |
0 |
24 |
24 |
24 |
24 |
24 |
0 |
0 |
0 |
0 |
0 |
inst2|rsp_xbar_mux_001|arb |
16 |
0 |
4 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|rsp_xbar_mux_001 |
1335 |
0 |
0 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|rsp_xbar_mux|arb|adder |
16 |
8 |
0 |
8 |
8 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
inst2|rsp_xbar_mux|arb |
8 |
0 |
4 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|rsp_xbar_mux |
447 |
0 |
0 |
0 |
115 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|rsp_xbar_demux_011 |
114 |
1 |
2 |
1 |
112 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst2|rsp_xbar_demux_010 |
114 |
1 |
2 |
1 |
112 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst2|rsp_xbar_demux_009 |
114 |
1 |
2 |
1 |
112 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst2|rsp_xbar_demux_008 |
114 |
1 |
2 |
1 |
112 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst2|rsp_xbar_demux_007 |
114 |
1 |
2 |
1 |
112 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst2|rsp_xbar_demux_006 |
114 |
1 |
2 |
1 |
112 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst2|rsp_xbar_demux_005 |
114 |
1 |
2 |
1 |
112 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst2|rsp_xbar_demux_004 |
114 |
1 |
2 |
1 |
112 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst2|rsp_xbar_demux_003 |
115 |
4 |
2 |
4 |
223 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
inst2|rsp_xbar_demux_002 |
115 |
4 |
2 |
4 |
223 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
inst2|rsp_xbar_demux_001 |
115 |
4 |
2 |
4 |
223 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
inst2|rsp_xbar_demux |
115 |
4 |
2 |
4 |
223 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
inst2|cmd_xbar_mux_003|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
inst2|cmd_xbar_mux_003|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|cmd_xbar_mux_003 |
225 |
0 |
0 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|cmd_xbar_mux_002|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
inst2|cmd_xbar_mux_002|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|cmd_xbar_mux_002 |
225 |
0 |
0 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|cmd_xbar_mux_001|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
inst2|cmd_xbar_mux_001|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|cmd_xbar_mux_001 |
225 |
0 |
0 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|cmd_xbar_mux|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
inst2|cmd_xbar_mux|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|cmd_xbar_mux |
225 |
0 |
0 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|cmd_xbar_demux_001 |
136 |
144 |
2 |
144 |
1333 |
144 |
144 |
144 |
0 |
0 |
0 |
0 |
0 |
inst2|cmd_xbar_demux |
128 |
16 |
10 |
16 |
445 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
inst2|rst_controller|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|rst_controller |
17 |
14 |
0 |
14 |
1 |
14 |
14 |
14 |
0 |
0 |
0 |
0 |
0 |
inst2|burst_adapter_001|altera_merlin_burst_adapter_uncompressed_only.the_ba |
87 |
3 |
5 |
3 |
85 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst2|burst_adapter_001 |
87 |
0 |
0 |
0 |
85 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|burst_adapter|altera_merlin_burst_adapter_uncompressed_only.the_ba |
96 |
3 |
5 |
3 |
94 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst2|burst_adapter |
96 |
0 |
0 |
0 |
94 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|limiter_001 |
226 |
0 |
0 |
0 |
235 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|limiter |
226 |
0 |
0 |
0 |
235 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|id_router_011|the_default_decode |
0 |
16 |
0 |
16 |
16 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
inst2|id_router_011 |
102 |
0 |
2 |
0 |
112 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|id_router_010|the_default_decode |
0 |
16 |
0 |
16 |
16 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
inst2|id_router_010 |
102 |
0 |
2 |
0 |
112 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|id_router_009|the_default_decode |
0 |
16 |
0 |
16 |
16 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
inst2|id_router_009 |
75 |
0 |
2 |
0 |
85 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|id_router_008|the_default_decode |
0 |
16 |
0 |
16 |
16 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
inst2|id_router_008 |
102 |
0 |
2 |
0 |
112 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|id_router_007|the_default_decode |
0 |
16 |
0 |
16 |
16 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
inst2|id_router_007 |
102 |
0 |
2 |
0 |
112 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|id_router_006|the_default_decode |
0 |
16 |
0 |
16 |
16 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
inst2|id_router_006 |
102 |
0 |
2 |
0 |
112 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|id_router_005|the_default_decode |
0 |
16 |
0 |
16 |
16 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
inst2|id_router_005 |
102 |
0 |
2 |
0 |
112 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|id_router_004|the_default_decode |
0 |
16 |
0 |
16 |
16 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
inst2|id_router_004 |
102 |
0 |
2 |
0 |
112 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|id_router_003|the_default_decode |
0 |
16 |
0 |
16 |
16 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
inst2|id_router_003 |
102 |
0 |
2 |
0 |
112 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|id_router_002|the_default_decode |
0 |
16 |
0 |
16 |
16 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
inst2|id_router_002 |
102 |
0 |
2 |
0 |
112 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|id_router_001|the_default_decode |
0 |
16 |
0 |
16 |
16 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
inst2|id_router_001 |
84 |
0 |
2 |
0 |
94 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|id_router|the_default_decode |
0 |
16 |
0 |
16 |
16 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
inst2|id_router |
102 |
0 |
2 |
0 |
112 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|addr_router_001|the_default_decode |
0 |
16 |
0 |
16 |
16 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
inst2|addr_router_001 |
102 |
0 |
6 |
0 |
112 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|addr_router|the_default_decode |
0 |
16 |
0 |
16 |
16 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
inst2|addr_router |
102 |
0 |
6 |
0 |
112 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|ledg_avalon_parallel_port_slave_translator_avalon_universal_slave_0_agent_rsp_fifo |
142 |
39 |
0 |
39 |
101 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
inst2|ledg_avalon_parallel_port_slave_translator_avalon_universal_slave_0_agent|uncompressor |
37 |
1 |
0 |
1 |
35 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst2|ledg_avalon_parallel_port_slave_translator_avalon_universal_slave_0_agent |
288 |
39 |
49 |
39 |
301 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
inst2|keys_avalon_parallel_port_slave_translator_avalon_universal_slave_0_agent_rsp_fifo |
142 |
39 |
0 |
39 |
101 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
inst2|keys_avalon_parallel_port_slave_translator_avalon_universal_slave_0_agent|uncompressor |
37 |
1 |
0 |
1 |
35 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst2|keys_avalon_parallel_port_slave_translator_avalon_universal_slave_0_agent |
288 |
39 |
49 |
39 |
301 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
inst2|lcd_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo |
115 |
39 |
0 |
39 |
74 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
inst2|lcd_avalon_lcd_slave_translator_avalon_universal_slave_0_agent|uncompressor |
37 |
1 |
0 |
1 |
35 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst2|lcd_avalon_lcd_slave_translator_avalon_universal_slave_0_agent |
186 |
13 |
25 |
13 |
194 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
inst2|seg74_avalon_parallel_port_slave_translator_avalon_universal_slave_0_agent_rsp_fifo |
142 |
39 |
0 |
39 |
101 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
inst2|seg74_avalon_parallel_port_slave_translator_avalon_universal_slave_0_agent|uncompressor |
37 |
1 |
0 |
1 |
35 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst2|seg74_avalon_parallel_port_slave_translator_avalon_universal_slave_0_agent |
288 |
39 |
49 |
39 |
301 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
inst2|seg30_avalon_parallel_port_slave_translator_avalon_universal_slave_0_agent_rsp_fifo |
142 |
39 |
0 |
39 |
101 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
inst2|seg30_avalon_parallel_port_slave_translator_avalon_universal_slave_0_agent|uncompressor |
37 |
1 |
0 |
1 |
35 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst2|seg30_avalon_parallel_port_slave_translator_avalon_universal_slave_0_agent |
288 |
39 |
49 |
39 |
301 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
inst2|switches_avalon_parallel_port_slave_translator_avalon_universal_slave_0_agent_rsp_fifo |
142 |
39 |
0 |
39 |
101 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
inst2|switches_avalon_parallel_port_slave_translator_avalon_universal_slave_0_agent|uncompressor |
37 |
1 |
0 |
1 |
35 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst2|switches_avalon_parallel_port_slave_translator_avalon_universal_slave_0_agent |
288 |
39 |
49 |
39 |
301 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
inst2|ledr_avalon_parallel_port_slave_translator_avalon_universal_slave_0_agent_rsp_fifo |
142 |
39 |
0 |
39 |
101 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
inst2|ledr_avalon_parallel_port_slave_translator_avalon_universal_slave_0_agent|uncompressor |
37 |
1 |
0 |
1 |
35 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst2|ledr_avalon_parallel_port_slave_translator_avalon_universal_slave_0_agent |
288 |
39 |
49 |
39 |
301 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
inst2|jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo |
142 |
39 |
0 |
39 |
101 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
inst2|jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|uncompressor |
37 |
1 |
0 |
1 |
35 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst2|jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent |
288 |
39 |
49 |
39 |
301 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
inst2|timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo |
142 |
39 |
0 |
39 |
101 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
inst2|timer_1_s1_translator_avalon_universal_slave_0_agent|uncompressor |
37 |
1 |
0 |
1 |
35 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst2|timer_1_s1_translator_avalon_universal_slave_0_agent |
288 |
39 |
49 |
39 |
301 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
inst2|timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo |
142 |
39 |
0 |
39 |
101 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
inst2|timer_0_s1_translator_avalon_universal_slave_0_agent|uncompressor |
37 |
1 |
0 |
1 |
35 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst2|timer_0_s1_translator_avalon_universal_slave_0_agent |
288 |
39 |
49 |
39 |
301 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
inst2|sram_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo |
63 |
41 |
0 |
41 |
20 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
inst2|sram_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo |
124 |
39 |
0 |
39 |
83 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
inst2|sram_avalon_sram_slave_translator_avalon_universal_slave_0_agent|uncompressor |
37 |
1 |
0 |
1 |
35 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst2|sram_avalon_sram_slave_translator_avalon_universal_slave_0_agent |
220 |
22 |
33 |
22 |
230 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
inst2|nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo |
142 |
39 |
0 |
39 |
101 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
inst2|nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent|uncompressor |
37 |
1 |
0 |
1 |
35 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst2|nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent |
288 |
39 |
49 |
39 |
301 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
inst2|nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent |
179 |
37 |
79 |
37 |
134 |
37 |
37 |
37 |
0 |
0 |
0 |
0 |
0 |
inst2|nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent |
179 |
37 |
79 |
37 |
134 |
37 |
37 |
37 |
0 |
0 |
0 |
0 |
0 |
inst2|ledg_avalon_parallel_port_slave_translator |
105 |
7 |
19 |
7 |
75 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
inst2|keys_avalon_parallel_port_slave_translator |
105 |
7 |
19 |
7 |
75 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
inst2|lcd_avalon_lcd_slave_translator |
52 |
6 |
20 |
6 |
22 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
inst2|seg74_avalon_parallel_port_slave_translator |
105 |
7 |
19 |
7 |
75 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
inst2|seg30_avalon_parallel_port_slave_translator |
105 |
7 |
19 |
7 |
75 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
inst2|switches_avalon_parallel_port_slave_translator |
105 |
7 |
19 |
7 |
75 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
inst2|ledr_avalon_parallel_port_slave_translator |
105 |
7 |
19 |
7 |
75 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
inst2|jtag_uart_avalon_jtag_slave_translator |
105 |
6 |
23 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
inst2|timer_1_s1_translator |
89 |
23 |
37 |
23 |
55 |
23 |
23 |
23 |
0 |
0 |
0 |
0 |
0 |
inst2|timer_0_s1_translator |
89 |
23 |
37 |
23 |
55 |
23 |
23 |
23 |
0 |
0 |
0 |
0 |
0 |
inst2|sram_avalon_sram_slave_translator |
70 |
6 |
3 |
6 |
56 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
inst2|nios2_qsys_0_jtag_debug_module_translator |
105 |
6 |
12 |
6 |
82 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
inst2|nios2_qsys_0_data_master_translator |
106 |
13 |
2 |
13 |
98 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
inst2|nios2_qsys_0_instruction_master_translator |
106 |
52 |
2 |
52 |
98 |
52 |
52 |
52 |
0 |
0 |
0 |
0 |
0 |
inst2|ledg |
43 |
0 |
26 |
0 |
41 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|keys |
47 |
0 |
32 |
0 |
33 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|timer_1 |
23 |
0 |
0 |
0 |
17 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|timer_0 |
23 |
0 |
0 |
0 |
17 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|lcd|Char_LCD_Init |
4 |
0 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|lcd|Char_LCD_Comm |
15 |
2 |
0 |
2 |
14 |
2 |
2 |
2 |
8 |
0 |
0 |
0 |
0 |
inst2|lcd |
14 |
0 |
1 |
0 |
14 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
inst2|seg74 |
43 |
0 |
1 |
0 |
60 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|seg30 |
43 |
0 |
1 |
0 |
60 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|switches |
61 |
0 |
38 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|ledr |
43 |
0 |
16 |
0 |
50 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|jtag_uart|the_lab1qsys_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|jtag_uart|the_lab1qsys_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|jtag_uart|the_lab1qsys_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram|altsyncram2 |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|jtag_uart|the_lab1qsys_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|jtag_uart|the_lab1qsys_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|jtag_uart|the_lab1qsys_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|jtag_uart|the_lab1qsys_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo |
13 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|jtag_uart|the_lab1qsys_jtag_uart_scfifo_r|rfifo|auto_generated |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|jtag_uart|the_lab1qsys_jtag_uart_scfifo_r |
13 |
0 |
1 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|jtag_uart|the_lab1qsys_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|jtag_uart|the_lab1qsys_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|jtag_uart|the_lab1qsys_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram|altsyncram2 |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|jtag_uart|the_lab1qsys_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|jtag_uart|the_lab1qsys_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|jtag_uart|the_lab1qsys_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|jtag_uart|the_lab1qsys_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo |
13 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|jtag_uart|the_lab1qsys_jtag_uart_scfifo_w|wfifo|auto_generated |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|jtag_uart|the_lab1qsys_jtag_uart_scfifo_w |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|jtag_uart |
38 |
10 |
23 |
10 |
34 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
inst2|sram |
40 |
0 |
0 |
0 |
40 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
inst2|nios2_qsys_0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2 |
24 |
0 |
0 |
0 |
111 |
0 |
0 |
0 |
24 |
0 |
0 |
0 |
0 |